A high-speed digital interface may be used to carry data within an electronic device or from one electronic device to another. In many scenarios, the data carried over the interface is synchronized to a clock signal of the sending device, which typically is not carried over the interface. In order to parse the data it receives, the receiving device will attempt to recreate the clock signal of the sending device. A so-called clock-and-data recovery (CDR) circuit may be used for this purpose.
A CDR circuit adjusts the frequency and phase of a local clock in the receiving device to achieve consistency with the various logic transitions of the data received. In high-speed applications, the CDR circuit must tolerate the effects of clock jitter in the sending and/or receiving clocks, as well as signal drift in the sent data. To this end, the CDR circuit may tally the clock pulses arriving early with respect to the data, versus the clock pulses arriving late. The relative tally is then shifted and added into a binary register. In this configuration, a chosen output transition of the register triggers advance of the local clock phase when late arrivals outnumber early arrivals by a threshold number; a complementary output transition triggers retard of the local clock phase when early arrivals outnumber late arrivals by the threshold number. The threshold number is programmable in this approach, inasmuch as any output bit of the register may be chosen to trigger advance or retard of the local clock phase. Naturally, however, the threshold is limited to integer powers of two.
In the CDR approach summarized above, the register bit chosen to trigger advance or retard of the local clock phase may be determined by an adjustable filter setting for the CDR circuit. A CDR circuit with a large filter setting (updating the clock phase on a high power of two) may react slowly to timing changes in the data, but will not overshoot the required clock phase. Conversely, a CDR circuit with a small filter setting (updating on a low power of two) will respond more quickly to timing changes in the data, but may overshoot the required clock phase, thereby introducing additional jitter. Accordingly, a filter setting that is either too high or too low for a given interface is undesirable, as it may limit the bandwidth of error-free transmission.